|
| #define | MIN(a, b) (a<b?a:b) |
| |
| #define | SQUIDMIB 1, 3, 6, 1, 4, 1, 3495, 1 |
| |
| #define | LEN_SQUIDMIB 8 |
| |
| #define | INSTANCE 0 |
| |
| #define | TIME_INDEX 1, 5, 60 |
| |
| #define | TIME_INDEX_LEN 3 |
| |
| #define | SQ_SYS SQUIDMIB, 1 /* cacheSystem group { squid 1 } */ |
| |
| #define | LEN_SQ_SYS LEN_SQUIDMIB+1 |
| |
| #define | SQ_CONF SQUIDMIB, 2 /* cacheConfig group { squid 2 } */ |
| |
| #define | LEN_SQ_CONF LEN_SQUIDMIB+1 |
| |
| #define | SQ_PRF SQUIDMIB, 3 /* cachePerformance group { squid 3 } */ |
| |
| #define | LEN_SQ_PRF LEN_SQUIDMIB+1 |
| |
| #define | SQ_NET SQUIDMIB, 4 /* cacheNetwork group { squid 4 } */ |
| |
| #define | LEN_SQ_NET LEN_SQUIDMIB+1 |
| |
| #define | SQ_MESH SQUIDMIB, 5 /* cacheMesh group { squid 5 } */ |
| |
| #define | LEN_SQ_MESH LEN_SQUIDMIB+1 |
| |
| #define | LEN_SYS LEN_SQ_SYS + 1 |
| |
| #define | LEN_SYS_INST LEN_SQ_SYS + 2 |
| |
| #define | LEN_CONF LEN_SQ_CONF + 1 |
| |
| #define | LEN_CONF_INST LEN_SQ_CONF + 2 |
| |
| #define | LEN_CONF_ST LEN_CONF + 1 |
| |
| #define | LEN_CONF_ST_INST LEN_CONF + 2 |
| |
|
| enum | {
SYS_START = 0
,
SYSVMSIZ = 1
,
SYSSTOR = 2
,
SYS_UPTIME = 3
,
SYS_END
} |
| |
| enum | {
CONF_START = 0
,
CONF_ADMIN = 1
,
CONF_VERSION = 2
,
CONF_VERSION_ID = 3
,
CONF_LOG_FAC = 4
,
CONF_STORAGE = 5
,
CONF_UNIQNAME = 6
,
CONF_END
} |
| |
| enum | {
CONF_ST_START = 0
,
CONF_ST_MMAXSZ = 1
,
CONF_ST_SWMAXSZ = 2
,
CONF_ST_SWHIWM = 3
,
CONF_ST_SWLOWM = 4
,
CONF_ST_END
} |
| |
| enum | {
PERF_START = 0
,
PERF_SYS = 1
,
PERF_PROTO = 2
,
PERF_END
} |
| |
| enum | {
PERF_SYS_START = 0
,
PERF_SYS_PF = 1
,
PERF_SYS_NUMR = 2
,
PERF_SYS_MEMUSAGE = 3
,
PERF_SYS_CPUTIME = 4
,
PERF_SYS_CPUUSAGE = 5
,
PERF_SYS_MAXRESSZ = 6
,
PERF_SYS_NUMOBJCNT = 7
,
PERF_SYS_CURLRUEXP = 8
,
PERF_SYS_CURUNLREQ = 9
,
PERF_SYS_CURUNUSED_FD = 10
,
PERF_SYS_CURRESERVED_FD = 11
,
PERF_SYS_CURUSED_FD = 12
,
PERF_SYS_CURMAX_FD = 13
,
PERF_SYS_END
} |
| |
| enum | {
PERF_PROTOSTAT_START
,
PERF_PROTOSTAT_AGGR = 1
,
PERF_PROTOSTAT_MEDIAN = 2
,
PERF_PROTOSTAT_END
} |
| |
| enum | {
PERF_PROTOSTAT_AGGR_START = 0
,
PERF_PROTOSTAT_AGGR_HTTP_REQ = 1
,
PERF_PROTOSTAT_AGGR_HTTP_HITS = 2
,
PERF_PROTOSTAT_AGGR_HTTP_ERRORS = 3
,
PERF_PROTOSTAT_AGGR_HTTP_KBYTES_IN = 4
,
PERF_PROTOSTAT_AGGR_HTTP_KBYTES_OUT = 5
,
PERF_PROTOSTAT_AGGR_ICP_S = 6
,
PERF_PROTOSTAT_AGGR_ICP_R = 7
,
PERF_PROTOSTAT_AGGR_ICP_SKB = 8
,
PERF_PROTOSTAT_AGGR_ICP_RKB = 9
,
PERF_PROTOSTAT_AGGR_REQ = 10
,
PERF_PROTOSTAT_AGGR_ERRORS = 11
,
PERF_PROTOSTAT_AGGR_KBYTES_IN = 12
,
PERF_PROTOSTAT_AGGR_KBYTES_OUT = 13
,
PERF_PROTOSTAT_AGGR_CURSWAP = 14
,
PERF_PROTOSTAT_AGGR_CLIENTS = 15
,
PERF_PROTOSTAT_AGGR_END
} |
| |
| enum | {
PERF_MEDIAN_START = 0
,
PERF_MEDIAN_TIME = 1
,
PERF_MEDIAN_HTTP_ALL = 2
,
PERF_MEDIAN_HTTP_MISS = 3
,
PERF_MEDIAN_HTTP_NM = 4
,
PERF_MEDIAN_HTTP_HIT = 5
,
PERF_MEDIAN_ICP_QUERY = 6
,
PERF_MEDIAN_ICP_REPLY = 7
,
PERF_MEDIAN_DNS = 8
,
PERF_MEDIAN_RHR = 9
,
PERF_MEDIAN_BHR = 10
,
PERF_MEDIAN_HTTP_NH = 11
,
PERF_MEDIAN_END
} |
| |
| enum | {
NET_START = 0
,
NET_IP_CACHE = 1
,
NET_FQDN_CACHE = 2
,
NET_DNS_CACHE = 3
,
NET_END
} |
| |
| enum | {
IP_START = 0
,
IP_ENT = 1
,
IP_REQ = 2
,
IP_HITS = 3
,
IP_PENDHIT = 4
,
IP_NEGHIT = 5
,
IP_MISS = 6
,
IP_GHBN = 7
,
IP_LOC = 8
,
IP_END
} |
| |
| enum | {
FQDN_START = 0
,
FQDN_ENT = 1
,
FQDN_REQ = 2
,
FQDN_HITS = 3
,
FQDN_PENDHIT = 4
,
FQDN_NEGHIT = 5
,
FQDN_MISS = 6
,
FQDN_GHBN = 7
,
FQDN_END
} |
| |
| enum | {
DNS_START = 0
,
DNS_REQ = 1
,
DNS_REP = 2
,
DNS_SERVERS = 3
,
DNS_END
} |
| |
| enum | {
MESH_START = 0
,
MESH_PTBL = 1
,
MESH_CTBL = 2
,
MESH_END
} |
| |
| enum | {
MESH_PTBL_START = 0
,
MESH_PTBL_INDEX = 1
,
MESH_PTBL_NAME = 2
,
MESH_PTBL_ADDR_TYPE = 3
,
MESH_PTBL_ADDR = 4
,
MESH_PTBL_HTTP = 5
,
MESH_PTBL_ICP = 6
,
MESH_PTBL_TYPE = 7
,
MESH_PTBL_STATE = 8
,
MESH_PTBL_SENT = 9
,
MESH_PTBL_PACKED = 10
,
MESH_PTBL_FETCHES = 11
,
MESH_PTBL_RTT = 12
,
MESH_PTBL_IGN = 13
,
MESH_PTBL_KEEPAL_S = 14
,
MESH_PTBL_KEEPAL_R = 15
,
MESH_PTBL_END
} |
| |
| enum | {
MESH_CTBL_START = 0
,
MESH_CTBL_ADDR_TYPE = 1
,
MESH_CTBL_ADDR = 2
,
MESH_CTBL_HTREQ = 3
,
MESH_CTBL_HTBYTES = 4
,
MESH_CTBL_HTHITS = 5
,
MESH_CTBL_HTHITBYTES = 6
,
MESH_CTBL_ICPREQ = 7
,
MESH_CTBL_ICPBYTES = 8
,
MESH_CTBL_ICPHITS = 9
,
MESH_CTBL_ICPHITBYTES = 10
,
MESH_CTBL_END
} |
| |
